1. Field of the Invention
The present invention relates generally to symmetric multi-processor (SMP) computer systems, and more particularly, to heterogeneous SMP computer systems.
2. Related Art
In symmetric multi-processor (SMP) computer systems, two or more processors share memory and IO devices, for example a display terminal. An operating system, generally stored in the shared memory, supports the scheduling of tasks among the various processors.
SMP systems permit parallel processing of tasks to increase system throughput. For instance, where an applications program requires a number of tasks to be performed or where several applications are running simultaneously, the operating system in an SMP system divides and schedules these tasks among the various processors in a system. An SMP system performs tasks in parallel, thereby increasing the number of tasks which can be executed in a given amount of time.
Operating systems such as Windows NT are available for supporting one or more processors in a symmetric multi-processing environment. These operating systems permit the processors to see the same memory space with each physical memory location in the memory space having an address which is common to all of the processors.
Operating systems exist for supporting various types of processors, including, for example, Intel 80X86, DEC Alpha, IBM/Motorola Power PC, and MIPS R4000. Current SMP hardware implementations and operating systems, however, support efficient execution of only a single processor family instruction set on a given platform. In other words, an Intel based X86 SMP system is not well suited to execute code compiled for a DEC Alpha system because current SMP systems are limited to using processors from only a single family of processors and often require that the processors even be of the same type within a particular family.
Computer users, however, often have multiple computing requirements, such as word processing, data processing, graphics generation and communications. Although applications program""s for these different computing requirements are available for various types of processors, a user is faced with a purchasing dilemma when a preferred application is not compatible with their existing processor. In such a case, the user must either substitute the less desirable program for the desired one or purchase a new computer having a processor which is compatible with the desired program. Similarly, an application which is compatible with a user""s processor may be priced significantly higher than a similar application which is not compatible with the user""s current processor. Again, the user must either buy the less desirable program or a new computer. Computer users are, therefore, restricted in their applications software choices by their processor.
Emulation systems are available for some processors which permit non-native instruction sets to be executed on the processor. This is a common practice on DEC Alpha systems when executing Intel 80X86 binaries. Essentially, an emulation program provides subroutines written in a processor""s native language permitting execution of non-native instructions. When the program loader detects a non-native application, it calls a native emulation program associated with the non-native application. The native emulation. program contains native code for performing the non-native instruction on the native processor and, possibly, for instructing the native processor to output data in a non-native communication protocol. Emulation of a program, however, is usually eight times or more slower than executing binary code directly on a native processor.
A single mode binary code file is a program compiled into native instructions for a single type of processor family. Mixed mode binary code files contain instruction sequences (for different functions or subroutines) for more than one type of processor or family of processors. For any given function or subroutine, however, binary code is provided for executing that function or subroutine on only one type of processor or family of processors.
Current SMP systems employ only a single type of processor or family of processors and execute only single mode binary code files. Also, programs compiled to execute on a single family of processors suffer from the same limitations as the processors they employ. Examples of such limitations include interrupt latency, byte ordering, floating point and integer performance. As a result, programmers are unable to take advantage of particular features from multiple families of processors.
What is needed, therefore, is a heterogenous symmetric multi-processor system (HSMP) employing heterogenous processors for executing a variety of types of binary code on native processors. An HSMP system should include an operating system for scheduling execution of various types of binary code on native processors, including both single mode binary code and mixed mode binary code.
The present invention provides a heterogenous symmetric multi-processor (HSMP) system and methods for operating the HSMP system.
In a preferred HSMP system, one or more processors from a first processor family are packaged on a single printed circuit card along with necessary bus interface converters for coupling the card to a common bus. Additional circuit cards include processors from other families of processors. These circuit cards are coupled to the common bus through additional bus interface converters. The bus provides each processor with access to common IO devices and memory.
An HSMP operating system (HSMP OS) controls scheduling operations on the HSMP system by maintaining separate ready queues for each family of processors. Each ready queue coordinates the execution of process threads for its associated family of processors.
The operating system supports scheduling of mixed-mode binary code as well as single mode binary code. Single mode binary code is code designed to run on only a specific processor or family of processors. Mixed mode binary code includes at least two types-of code, a first type of code designed to run on a first type of processor or family of processors and a second type of code designed to run on a second type of processor or family or processors. With mixed mode binary code, a programmer can take advantage of strengths or particular capabilities of different processors within a single application program.
In the HSMP OS, when a thread is created, the HSMP OS determines the initial processor family to associate with the thread based on the binary code stream that the thread will begin executing.
In an alternative embodiment the HSMP OS is itself a single mode binary code file and includes specialized interfaces to enable a thread to transition between processor families across kernel service calls. This involves scheduling the kernel request on a processor which is native to the HSMP OS and rescheduling the non-native processor to execute some other thread which is in the ready queue for that processor family. The reverse transition occurs when the kernel service call completes.
Three methods are disclosed for notifying, an operating system when a mixed mode binary file requires a change in processor family to continue instruction stream execution.
In a first method, a mixed mode binary file: includes an instruction which is common to all the processors in the system and which, when executed, will not cause adverse side effects but will cause an unexpected entry into the operating system (e.g. an invalid instruction). This commonly invalid instruction serves as a signal to the operating system that a processor switch may be required.
In a second method, a mixed mode binary file includes special jacket libraries containing code designed for a particular processor or family of processors. Each jacket library includes an indicator for indicating which processor is required for executing the code contained in the jacket library.
In a third method, a new instruction is included in a mixed mode binary file which is interpreted identically by all of the processors in the system. The new instruction includes an operand for identifying which of the processors is required for executing a stream of binary code which follows the operand.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.